1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of forming a contact hole connecting to a silicon film of a semiconductor device having a structure of an erasable programmable read-only memory (EPROM).
2. Description of the Related Art
A self-alignment contact (SAC) etching technology has been used in order to create a minute contact hole and to provide a margin for an alignment of the photolithography process in the above-mentioned semiconductor device (refer to, for example, Japanese Patent Kokai No. 2001-127039). According to this technology, during a contact formation process, a gate electrode is covered with a nitride film so that the nitride film serves as a stopper film.
On the other hand, a dry etching method for the semiconductor device is known, in which a contact hole is formed to penetrate insulation films consisting of a non-doped silicate glass (NSG) film and a boron phosphorus silicate glass (BPSG) film laminated on a silicon substrate, and then a damaged layer of the silicon substrate at the bottom of the contact hole and a coated film on an inner wall of the contact hole are removed while preventing the insulation films of the laminated structure from side-etching. According to this method, by applying high-frequency power to a mixed gas of oxygen and carbon fluoride, it is possible to remove the damaged layer and the coated film and accurately form a contact hole having a smoothly tapered inner wall with no stepped section (refer to, for example, Japanese Patent Kokai No. 6-283460).
Further, another dry etching technique is known using a dry etching apparatus of a narrow gap system, in which a mixed gas of CF4, CHF3 and Ar is used as a dry etching gas for etching an interlayer insulation film (refer to, for example, Japanese Patent Kokai No. 5-102107). This technique forms a minute and deep contact hole having a tapered slope, viewed in cross section, with an aspect ratio greater than 1, by forming a protection film on a side surface of the contact hole.
The above-mentioned etching process described in Japanese Patent Kokai No. 2001-127039, i.e., the process using the SAC technique in which the gate electrode is covered with the nitride film so that the nitride film serves as a stopper film, requires the process to cover the gate electrode with the nitride film. Accordingly, the etching process has a problem in that physical-chemical properties of the gate electrode may change and that adjustment of an electrical characteristic, such as resistance or capacitance, may be difficult.
When it is impossible to cover the nitride film, a forward tapered slope is generally formed, which however may cause a problem when the lithography size is less than about 0.20 μm. For example, in the case of a reactive ion etching (RIE) employing a mixed gas of CHF3 and CO, the contact hole may have a so-called bow shape, i.e., a barrel shape, or the etching does not proceed when the contact hole reaches a certain depth due to deposition of a reaction product on the bottom. On the other hand, in the case of a mixed gas including CO and O2, the contact hole may easily provide a vertical slope, which may unfavorably connect to the gate electrode. Furthermore, in the case of patterning a large area, the silicon substrate may have a roughly etched situation, which decreases accuracy of the alignment for the photolithography and decreases the measurement accuracy for an alignment.
The above-mentioned dry etching method described in Japanese Patent Kokai No. 6-283460, which forms the contact hole to penetrate the insulation films of the NSG film and the BPSG film laminated on the silicon substrate, uses a mixed gas of oxygen and carbon fluoride as well as oxygen gas in order to remove the damaged layer and the coated film generated during the formation of the contact hole mentioned above. Accordingly, there is a problem in that a surface of the silicon substrate has a roughly etched condition, which decreases accuracy of the alignment for photolithography and decreases measurement accuracy for the alignment.
The above-mentioned dry etching method described in Japanese Patent Kokai No. 5-102107 creates the protection film on the side face of the contact hole, and therefore a process to remove the protection film on the side face of the contact hole is necessary after the etching process. Accordingly, there is a problem in that operation of the method is complicated, and that the surface of the silicon substrate is damaged, thereby decreasing the accuracy.